To boldly big-endian where no one has big-endianded before

The RISC-V Privileged ISA specification, allows for controlling the core data endian (the order in which the data is stored in memory) at runtime, using bits in the STATUS register. However, it is not currently supported in any commercially available hardware or in emulators, such as QEMU. Since Codethink has a history of bringing big-endian support to traditionally little-endian processor architectures, a project to investigate the new bits on RISC-V was proposed.

There are still applications where the way data is stored matters, such as the protocols that move data across the Internet, which are defined as big-endian. So when a little-endian system needs to inspect or modify a network packet, it has to swap the big-endian values to little-endian and back, a process that can take as many as 10-20 instructions on a RISC-V target which doesn't implement the Zbb extension.

It was soon determined that there was little current support. However, with some patching, we could run a simple system in big-endian using current open-source technology. Since we could not find existing hardware which supported big endian operation, QEMU would be the base of the testing.

So far, we have patches for buildroot for a big-endian build, QEMU updates to add the necessary status bits and change the load/store code to go from little to big-endian, and updates for projects such as OpenSBI, Linux Kernel, and uclibc-ng to allow building a bootable buildroot image. You can find all patch submissions on the project GitLab.

There are still open issues, such as bugs in buildroot building with glibc, floating point and vector endianness, and kvmtool (endian control and PCI accesses for virtio), which we may address in a future project to expand support.

For more information, project source, patch submissions, and logs can be found on our GitLab: https://gitlab.com/CodethinkLabs/riscv_bigendian